The present invention relates to a digital-analog converting circuit (called D/A converting circuit, hereinafter), which may be incorporated in a semiconductor integrated circuit, having voltage-dividing resistors.
FIG. 4 is an explanatory diagram schematically showing a construction of a conventional D/A converting circuit 40. The D/A converting circuit 40 is a circuit with a 3-bit resolution. Essentially, in the D/A converting circuit 40, 23=8 resistors R having equal resistant values are connected in series between a reference potential terminal Vref and a ground terminal GND. The reference potential terminal Vref supplies a reference potential. The ground potential supplies a ground potential. When a digital signal (code) is input to a decoder circuit (not shown), one of switches SW0 to SW7 is selected and is turned on under the control of the decoder circuit. One of levels of nodes N0 to N7 corresponding to the ON switch is output from an output terminal OUT through an amplifier AMP. Thus, the reference potential and the ground potential are equally divided into eight so as to convert the digital signal to a desired analog signal. A PMOS transistor PMOS is connected between the reference potential terminal and the resistors R. The PMOS transistor PMOS is a switch for inhibiting an operation of the circuit and for shutting off current consumption in response to an enable signal ENB.
Generally, as shown in FIG. 5, the switches SW0 to SW7 are implemented by analog switches. Each of the analog switches is a combination of a P-channel type MOS transistor (called PMOS transistor, hereinafter) PMOS and an N-channel type MOS transistor (called, NMOS transistor, hereinafter) NMOS. By combining the PMOS transistor and the NMOS transistor, the ON resistances of the switches can be closer to a constant value. FIGS. 6A to 6C are explanatory diagrams each showing a relationship between a potential to be applied to a MOS transistor and an ON resistance of the MOS transistor. FIG. 6A shows an ON resistance of the PMOS transistor. FIG. 6B shows an ON resistance of the NMOS transistor. FIG. 6C shows a composite resistance of the ON resistances of the PMOS transistor and NMOS transistor.
However, the conventional D/A converting circuit has problems regarding the conversion precision and the conversion speed.
As shown in FIG. 6C, the composite resistance of ON resistances of the analog switches is not completely constant and depends on the input side potential. In the conventional D/A converting circuit, the nodes N0 to N7 corresponding to the switches SW0 to SW7 have different potentials from each other. Thus, the composite resistances of the ON resistances of the switches are not constant. As a result, the D/A conversion precision can be hardly improved.
Furthermore, as described above, the analog switches have the ON resistances. Due to the ON resistances and the parasitic capacitance within the circuit, the voltage level shifting in the output side takes time. Therefore, the conversion speed can be hardly improved.